1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor memory device including redundancy memory cells.
2. Description of the Related Art
In general, semiconductor memory devices such as Double Data Rate Synchronous DRAM (DDR SDRAM) include a large number of memory cells. As semiconductor memory devices become more highly integrated, the number of memory cells further increases. When a defect occurs in one of the memory cells, the semiconductor memory device cannot perform as intended and must therefore be discarded, which hurts product yield. To avoid this problem, semiconductor memory devices have redundancy memory cells in addition to normal memory cells.
Redundancy memory cells substitute for defective memory cells (hereafter, a ‘repair-target memory cell’). More specifically, when accessing the repair-target memory cell during a read/write operation, the redundancy memory cell is accessed instead of the repair-target memory cell. Thus, when an address corresponding to the repair-target memory cell is input, the semiconductor memory device accesses the redundancy memory cell instead of the repair-target memory cell, a process known as a ‘repair operation’. Through repair operations, semiconductor memory devices can continue to operate even with defective memory cells.
In addition to redundancy memory cells, additional circuits such as a repair fuse circuit are required to perform repair operations. Repair fuse circuits store addresses of repair-target memory cells (hereafter, referred to as ‘repair target address’), and include a multiple fuses. Each of the fuses is programmed with a repair target address. The programming includes a series of operations for storing state information in the fuse. For example, programming may include storing a repair target address in the fuse. Through the fuse programming, access to the repair-target memory cell is routed to the redundancy memory cell.
There are two methods for programming state information in fuses, a physical method and an electrical method.
The physical method programs the fuses using a laser beam to physically cut the fuses. Fuses for the physical method are referred to as physical type fuses. Since the electrical connection of the fuse is cut using a laser beam, they are also referred to as laser blown fuses. Because of their nature, physical type fuses can only be programmed in the wafer state and it is too late once they have been packed.
The electrical method programs state information by rupturing fuses (known as “electrical type fuses”) using a high voltage. Electrical fuses can be classified into anti-type fuses and blowing type fuses. Anti-type fuses go from an open state to a short state, and blowing type fuses go from a short state to an open state. Programming can be performed on electrical type fuses in both the package state and the wafer state, unlike physical type fuses. Semiconductor memory devices go through many test operations before they are commercialized. Only semiconductor memory devices having passed through all of the test operations are sold to consumers. The purpose of the testing operations to ensure the devices operate properly. Test operations are performed at every step of the fabrication process so that costs are not incurred by further processing of defective products.
Test operations for normal memory cells and redundancy memory cells will now be briefly described.
First, during a test operation, test data are stored in normal memory cells and redundancy memory cells, and the test data is read out to determine whether the normal and redundancy memory cells are working properly. Output of data will now be described. The normal word lines, each coupled to normal memory cells, are sequentially activated in response to test addresses which are sequentially enabled, and word lines coupled to redundancy memory cells are also sequentially activated in response to the test addresses which are sequentially enabled. The activation of the normal and redundancy word lines indicates that test data stored in memory cells coupled to an activated word line can be outputted to the outside. The outputted test data is analyzed to detect the repair target memory cells. Then, the repair target address corresponding to the detected repair target memory cells is programmed into the fuses. The programmed target address, that is, repair information, is provided to the proper circuit during a normal operation or test operation.